View AT24C64A-14_8380185.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? standard-voltage operation ?2.7(v cc =2.7vto5.5v) ? internally organized 409 6 x 8 (32k), 819 2 x 8 (64k) ? automotive temperature range ?40 ? c to +125 ? c ? two-wire serial interface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 400 khz clock rate ? write protect pin for hardware data protection ? 32-byte page write mode (partial page writes allowed) ? self-timed write cycle (5 ms max) ? high reliability ? endurance: 1 million write cycles ? data retention: 100 years ? lead-free/halogen-free devices available ? 8-lead jedec soic and 8-lead tssop packages description the at24c32a/64a provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (eeprom) organized as 4096/8192 words of 8 bits each. the device?s cascadable feature allows up to 8 devices to share a common two- wire bus. the device is optimized for use in many automotive applications where low power and low voltage operation are essential. the at24c32a/64a is available in space saving 8-lead jedec soic and 8-lead tssop packages and is accessed via a 2-wire serial interface and is available in a 2.7v (2.7v to 5.5v) version. table 1. pin configuration pin name function a0 ? a2 address inputs sda serial data scl serial clock input wp write protect two-wire automotive serial eeprom 32k (4096 x 8) 64k (8192 x 8) at24c32a (1) at24c64a 1. at24c32a not recommended for new design; replaced by at24c32d automotive. 2. at24c64a not recommended for new design; replaced by at24c64d automotive. 5120d?seepr?6/08 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-lead tssop 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda
2 5120d?seepr?6/08 at24c32a/64a figure 1. block diagram absolute maximum ratings* operating temperature ................................ ?55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature.................................... ?65 ? c to +150 ? c voltage on any pin with respect to ground ....................................?1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 5120d?seepr?6/08 at24c32a/64a pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/addresses (a2, a1, a0): the a2, a1 and a0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other at24cxx devices. when the pins are hardwired, as many as eight 32k/64k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). if the pins are left floating, the a2, a1 and a0 pins will be internally pulled down to gnd if the capaci- tive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends connecting the address pins to gnd. write protect (wp): the write protect input, when connected to gnd, allows normal write operations. when wp is connected high to v cc , all write operations to the memory are inhibited. if the pin is left floating, the wp pin will be internally pulled down to gnd if the capacitive cou- pling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends connecting the pin to gnd. switching wp to v cc prior to a write operation creates a software write protect function. memory organization at24c32a/64a, 32k/64k serial eeprom: the 32k/64k is internally organized as 128/256 pages of 32 bytes each. random word addressing requires a 12/13-bit data word address.
4 5120d?seepr?6/08 at24c32a/64a note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from t a =25 ? c,f=1.0 mhz, v cc = +2.7v to +5.5v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o =0v c in input capacitance (a 0 ,a 1 ,a 2 , scl) 6 pf v in =0v table 3. dc characteristics applicable over recommended operating range from: t a = ? 40 ? c to +125 ? c,v cc = +2.7v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max units v cc3 supply voltage 2.7 5.5 v i cc1 supply current v cc = 5.0v read at 400 khz 0.4 1.0 ma i cc2 supply current v cc = 5.0v write at 400 khz 2.0 3.0 ma i sb standby current v cc = 2.7v v in =v cc or v ss 1.0 3.0 a v cc = 5.0v 3.0 5.0 i li input leakage current v in =v cc or v ss 0.10 3.0 a i lo output leakage current v out =v cc or v ss 0.05 3.0 a v il (1) input low level ?0.6 v cc x 0.3 v v ih (1) input high level v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc =3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc =1.8v i ol = 0.15 ma 0.2 v
5 5120d?seepr?6/08 at24c32a/64a notes: 1. this parameter is ensured by characterization only. table 4. ac characteristics applicable over recommended operating range from t a = ? 40 ? c to +125 ? c, v cc = +2.7v to +5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter at24c32a/at24c64a units 2.7v ? 5.5v min max f scl clock frequency, scl 400 khz t low clock pulse width low 1.2 s t high clock pulse width high 0.6 s t i noise suppression time (1) 50 ns t aa clock low to data out valid 0.1 0.9 s t buf time the bus must be free before a new transmission can start (1) 1.2 s t hd.sta start hold time 0.6 s t su.sta start set-up time 0.6 s t hd.dat data in hold time 0 s t su.dat data in set-up time 100 ns t r (1) inputs rise time 0.3 s t f (1) inputs fall time 300 ns t su.sto stop set-up time 0.6 s t dh data out hold time 50 ns t wr write cycle time 5 ms endurance (1) 5.0v, 25 ? c, page mode 1m write cycles
6 5120d?seepr?6/08 at24c32a/64a device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (refer to data valid- ity timing diagram). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 5 on page 8 ). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see fig- ure 5 on page 8 ). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowl- edge that it has received each word. standby mode: the at24c32a/64a features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) clock up to 9 cycles, (b) look for sda high in each cycle while scl is high and then (c) create a start condition as sda is high.
7 5120d?seepr?6/08 at24c32a/64a figure 2. bus timing scl: serial clock, sda: serial data i/o figure 3. write cycle timing scl: serial clock, sda: serial data i/o note: 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. figure 4. data validity t wr (1) stop condition start condition wordn ack 8th bit scl sda
8 5120d?seepr?6/08 at24c32a/64a figure 5. start and stop definition figure 6. output acknowledge
9 5120d?seepr?6/08 at24c32a/64a device addressing the 32k/64k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see figure 7 on page 11 ). the device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. this is common to all 2-wire eeprom devices. the 32k/64k uses the three device address bits a2, a1, a0 to allow as many as eight devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a2, a1, and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/write operation select bit. a read operation is ini- tiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the device will return to standby state. noise protection: special internal circuitry placed on the sda and scl pins prevent small noise spikes from activating the device. data security: the at24c32a/64a has a hardware data protection scheme that allows the user to write protect the entire memory when the wp pin is at v cc . write operations byte write: a write operation requires two 8-bit data word addresses following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 8 on page 11 ). page write: the 32k/64k eeprom is capable of 32-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must ter- minate the page write sequence with a stop condition (see figure 9 on page 11 ). the data word address lower five bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the fol- lowing byte is placed at the beginning of the same page. if more than 32 data words are transmitted to the eeprom, the data word address will ?roll over? and previous data will be overwritten. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero, allowing the read or write sequence to continue.
10 5120d?seepr?6/08 at24c32a/64a read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page, to the first byte of the first page. the address ?roll over? during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condition (see figure 10 on page 11 ). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a follow- ing stop condition (see figure 11 on page 12 ). sequential read: sequential reads are initiated by either a current address read or a ran- dom address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?roll over? and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see figure 12 on page 12 ).
11 5120d?seepr?6/08 at24c32a/64a figure 7. device address figure 8. byte write figure 9. page write notes: 1. * = don?t care bits 2. ? = don?t care bits for the 32k figure 10. current address read
12 5120d?seepr?6/08 at24c32a/64a figure 11. random read note: 1. * = don?t care bits figure 12. sequential read
13 5120d?seepr?6/08 at24c32a/64a notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. 2. ?q? designates green package and rohs compliant. 3. at24c32a not recommended for new design; replaced by at24c32d automotive. at24c32a ordering information (1) ordering code package operation range at24c32an-10sq-2.7 (2) (3) at24c32a-10tq-2.7 (2) (3) 8s1 8a2 lead-free/halogen-free/ automotive (?40 ? c to 125 ? c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) options ? 2.7 low voltage (2.7v to 5.5v)
14 5120d?seepr?6/08 at24c32a/64a notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. 2. ?q? designates green package and rohs compliant. at24c64a ordering information (1) ordering code package operation range at24c64an-10sq-2.7 (2) at24c64a-10tq-2.7 (2) 8s1 8a2 lead-free/halogen-free/ automotive (?40 ? c to 125 ? c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 4.4mm body, plastic thin shrink small outline package (tssop) options ? 2.7 low voltage (2.7v to 5.5v)
15 5120d?seepr?6/08 at24c32a/64a package drawings 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 3/17/05 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 c common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0? ? 8? ? ? e e 1 1 n n top view top view c c e1 e1 end view a a b b l l a1 a1 e e d d side view side view
16 5120d?seepr?6/08 at24c32a/64a 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances , datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
17 5120d?seepr?6/08 at24c32a/64a revision history revision history revision date comments 5120d 8/2013 at24c64a not recommended for new design; replaced by at24c64d automotive. 5120d 8/2012 at24c32a not recommended for new design; replaced by at24c32d automotive. 5120d 6/2008 implemented revision history.
5120d?seepr?6/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support s_eeprom@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or inciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to s pecifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specifica lly provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others, are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

▲Up To Search▲

Price & Availability of AT24C64A-14

	To Download AT24C64A-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .